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An improved high speed, and low voltage CMOS current mode logic latch

  • Mixed Signal Letter
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Abstract

A high-speed, low voltage CMOS current mode logic (CML) latch, that has high input, and output voltage dynamic ranges, is proposed in this paper. The input common-mode voltage, and the output voltage dynamic range behavior are analyzed for the proposed latch and the most common (or typical) latch. Both CML latch structures were designed in a 0.18 \(\upmu\)m RFCMOS technology with a nominal voltage \(V_{DD}=1.8\) V. The output voltage errors, which the main cause is due to input voltage variations, even when the circuit is in latch mode, are analyzed in this paper. The post-layout results, using a clock frequency at 10 GHz, and the same bias current of 6 mA for both circuits shows an increment of 60 % for the output voltage swing in the proposed latch versus the typical latch. Besides, this topology being more robust it can be used for higher frequencies up to 20 GHz.

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Authors and Affiliations

  1. Electronic Circuit Design Department, Instituto Nacional de Astrofísica, Óptica y Electrónica, Luis Enrique Erro No. 1, Tonantzintla, Puebla, Mexico

    Oscar Lozada & Guillermo Espinosa

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  1. Oscar Lozada
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  2. Guillermo Espinosa
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Correspondence to Oscar Lozada.

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Lozada, O., Espinosa, G. An improved high speed, and low voltage CMOS current mode logic latch. Analog Integr Circ Sig Process 90, 247–252 (2017). https://doi.org/10.1007/s10470-016-0875-1

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  • DOI: https://doi.org/10.1007/s10470-016-0875-1

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