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Frequency compensation of two stage CMOS circuit using negative capacitance and flipped voltage follower

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Abstract

This paper presents a new and compact two stage CMOS structure with enhanced gain-bandwidth product (GBW) and high slew rate. The frequency compensation technique employed here comprises of a negative capacitance cell and a flipped voltage follower (FVF). The use of negative capacitance lowers the parasitic capacitance of preceding stage and thereby achieves significant improvement in GBW. The FVF acts as a voltage buffer and exploits pole-zero cancellation technique. The required compensation capacitor is very small so it can save chip area. The workability of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. The simulated results show a GBW of 1.2 GHz and average slew rate of 88 V/µs with a power consumption of 6.3 mW.

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Authors and Affiliations

  1. ECE Department, Netaji Subhash Institute of Technology, New Delhi, 110078, India

    Urvashi Bansal, Maneesha Gupta & Urvashi Singh

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  1. Urvashi Bansal
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  2. Maneesha Gupta
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  3. Urvashi Singh
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Correspondence to Maneesha Gupta.

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Bansal, U., Gupta, M. & Singh, U. Frequency compensation of two stage CMOS circuit using negative capacitance and flipped voltage follower. Analog Integr Circ Sig Process 90, 175–188 (2017). https://doi.org/10.1007/s10470-016-0857-3

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  • DOI: https://doi.org/10.1007/s10470-016-0857-3

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