Abstract
A data-dependent write-assist dynamic (DDWAD) SRAM cell is proposed to reduce the power consumption and enhance the relaibility against process, voltage, temperature variation and aging effect under static stress. The cell has distinct read and write circuits with single bit line for respective operations which improve the read stability. In the cell, write operation is performed using separate write signal WS instead of wordline WL. The write signal WS is introduced to reduce the discharging actvity at the write bit line BL to reduce the dynamic power consumption. The latch property of the cell is disabled during write operation to flip the data faster at the storage nodes. The proposed design approach provides high immunity to the data-dependent bit line leakage and results in lower voltage drop on BL, lower leakage current and lower parasitic capacitance. The proposed cell consumes approximately 60.4 % lower write power and 52.8 % read power compared to the other cells. The storage node does not float during read operation and thus cell is not sensitive to any positive noise. The data in the cell can be maintained even if the power supply is reduced to 300 mV.
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References
Kulkarni, J. P., Kim, K., & Roy, K. (2007). A 160 mV robust schmitt trigger based subthreshold SRAM. IEEE Journal of Solid-State Circuits, 42(10), 2303–2313.
Verma, N., & Chandrakasan, A. P. (2008). A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy. IEEE Journal of Solid-State Circuits, 43(1), 141–149.
Teman, A., Pergament, L., Cohen, O., & Fish, A. (2011). A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM). IEEE Journal of Solid State of Circuits, 46(11), 2713–2726.
Tu, M.-H., Lin, J.-Y., Tsai, M.-C., Lu, C.-Y., Lin, Y.-J., Wang, M.-H., et al. (2012). A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing. IEEE Journal of Solid-State Circuits, 47(6), 1469–1482.
Hu, V. P.-H., Fan, M.-L., Su, P., & Chuang, C.-T. (2013). Threshold voltage design of UTB SOI SRAM with improved stability/variability for ultralow voltage near subthreshold operation. IEEE Transactions on Nanotechnology, 12(4), 524–531.
Hassanzadeh, Z. M. S., Hajsadeghi, K., & Saeidi R. (2013). “A 32 kb 90 nm 9T-cell sub-threshold SRAM with improved read and write SNM”. In 2013 8th International Conference on Design and Technology Systems in Nanaoscale Era (DTIS) (pp. 104–107).
Chang, M.-F., Wu, J.-J., Chen, K.-T., Chen, Y.-C., Chen, Y.-H., Lee, R., et al. (2010). A differential data-aware power-supplied (D2AP) 8T SRAM Cell with expanded write/read stabilities for lower VDDmin applications. IEEE Journal of Solid-State Circuits, 45(6), 1234–1245.
Lin, C.-W., Huang, C.-Y., & Chao, M. C-T. (2013). Testing of a low-VMIN data-aware dynamic-supply 8T SRAM. In IEEE 31st VLSI Test Symposium (VTS), Berkeley, CA, April 29–May 2 2013. pp. 1–6.
Chen, C.-F., Chang, T.-H., Chen, L.-F., Chang, M.-F., & Yamauchi, H. (2013). “A 210 mV 7.3 MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency”. In Proceedings of the Symposium on VLSI Technology (VLSIT).
Chiu, Y.-W., Hu, Y.-H., Tu, M.-H., Zhao, J.-K., Jou, S.-J., & Chuang, C.-T. (2013). “A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist”. In Proceeding of the IEEE International Symposium on Low Power Electronics and Design (ISLPED).
Sun, Y., Jiao, H., & Kursun, V. (2014). “A novel robust and low-leakage SRAM cell with nine carbon nanotube transistors,”. In Proceedings of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
Singh, A. K., Seong, M. M., & Prabhu, C. M. R. (2014). A data aware (DA) 9T SRAM cell for low power consumption and improved stability. International Journal of Circuit Theory and Applications, 42(9), 956–966.
Chang, M.-F., Chang, S.-W., Chou, P.-W., & Wu, W.-C. (2011). A 130 mV SRAM with expanded write and read margins for subthreshold applications. IEEE Journal of Solid-State Circuits, 46(2), 520–529.
Acknowledgement
The authors are thankful to MOSTI-Malaysia for providing the financial assistance through e-Science Fund (03-02-01 SF 0203) to carry out this work.
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Singh, A.K., Saadatzi, M. & Venkataseshaiah, C. Design of a single-ended energy efficient data-dependent-write-assist dynamic (DDWAD) SRAM cell for improved stability and reliability. Analog Integr Circ Sig Process 90, 411–426 (2017). https://doi.org/10.1007/s10470-016-0840-z
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DOI: https://doi.org/10.1007/s10470-016-0840-z