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A background split algorithm for high speed pipelined ADCs

  • Mixed Signal Letter
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Abstract

The non-ideal problem, include transfer function gain errors and timing offset between channels, seriously restrict pipelined analog-to-digital converters (ADCs) sampling rate upgrade. This letter analyzes these sources of errors and the effect they have on split architecture. Using Taylor approximation and the digital differentiator filter in a hybrid LMS algorithm, the new method does not need any additional analog circuitry, does not perturb the output samples, and does not require strictly well matched layout of signal path between two channels. Behavioral simulation results demonstrate that the proposed calibration technique can significantly improve signal-to-noise and distortion ratio and spurious free dynamic range performance from 63.8 to 79.8 dB and 65.7 to more than 90.0 dB, respectively, for a 13-bit 500 MS/s pipelined ADC.

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61234002, 61322405, 61574103,61574105).

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, 2 Taibai Road, Xi’an, 710071, People’s Republic of China

    Siwan Dong, Zhangming Zhu, Minjie Liu & Yintang Yang

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  1. Siwan Dong
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  2. Zhangming Zhu
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  3. Minjie Liu
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  4. Yintang Yang
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Correspondence to Zhangming Zhu.

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Dong, S., Zhu, Z., Liu, M. et al. A background split algorithm for high speed pipelined ADCs. Analog Integr Circ Sig Process 88, 173–180 (2016). https://doi.org/10.1007/s10470-016-0753-x

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  • DOI: https://doi.org/10.1007/s10470-016-0753-x

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