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Analysis and modeling of response of external noise in oscillators

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Abstract

In this study, the influence of external-voltage noise on voltage-controlled oscillators (VCOs) is investigated. The phase error is derived using the extended phase domain response of the oscillators based on the impulse sensitivity function. We found that the frequency properties of the noise sensitivity strongly depend on the circuit configuration of the VCO. We applied these results to the linear model of a phase-locked loop (PLL) and conducted a numerical simulation. The simulation result showed that the generation of the phase error depends on the timing of impulse noise and the bandwidth of the PLL. The test chip for verification is designed and fabricated with a standard CMOS process.

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Acknowledgments

The authors would like to thank Shinji Shimizu and Koichiro Hida for their kind support in conducting the numerical analysis and the circuit simulation. This work was supported by STARC FS No. 1304 and the VLSI Design and Education Center (VDEC), The University of Tokyo, in collaboration with Cadence Corporation.

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  1. Graduate School of Engineering, Osaka Institute of Technology, Osaka, Japan

    Tsutomu Yoshimura & Takao Kihara

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  1. Tsutomu Yoshimura
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  2. Takao Kihara
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Correspondence to Tsutomu Yoshimura.

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Yoshimura, T., Kihara, T. Analysis and modeling of response of external noise in oscillators. Analog Integr Circ Sig Process 87, 313–325 (2016). https://doi.org/10.1007/s10470-015-0661-5

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