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On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs

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Abstract

It has recently shown how a constant dc offset between two low-quality test signals can be used to test the integral nonlinearity (INL) of A/D converters (ADCs) without an accurate test stimulus, and how the same method can be used to test the INL of D/A converters (DACs) as well. We propose here an on-chip offset generator for producing the constant offset and analyse its limitations. Experimental tests on the 122 × 22 μm2 offset generator fabricated in 130 nm CMOS process show that it can be used to test the INL of 12-b DACs and ADCs. The generator is rail-to-rail capable so that almost the whole input/output range of converters can be tested. Moreover, if the proposed offset generator is used in a ratiometric test setup as proposed here as well, the influence of a reference voltage drift on measurement accuracy is cancelled out. Because of its small size, simple design, rail-to-rail capability and immunity to reference voltage changes, the proposed offset generator is well suited for built-in self-test usage.

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Authors and Affiliations

  1. Department of Electrical and Information Engineering, University of Oulu, Oulu, Finland

    Esa Korhonen & Juha Kostamovaara

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  1. Esa Korhonen
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  2. Juha Kostamovaara
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Correspondence to Esa Korhonen.

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Korhonen, E., Kostamovaara, J. On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs. Analog Integr Circ Sig Process 67, 21–29 (2011). https://doi.org/10.1007/s10470-010-9496-2

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  • DOI: https://doi.org/10.1007/s10470-010-9496-2

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