Abstract.
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for instruction wakeup, which uses a multi-block instruction queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Palacharla, S.: Complexity effective Superscalar processors, PhD Thesis, University of Wisconsin, Madison (1998)
Buyoktusunoglu, A., Shuster, S.E., Brooks, D., Bose, P., Cook, P.W., Albonesi, D.H.: An Adaptive Issue Queue for Reduced Power at High Performance. In: Workshop on Power Aware Computer Systems, in conjunction with ASPLOS-IX (November 2000)
Folegnani, D., González, A.: Energy Effective Issue Logic. In: Proceedings of 28th Annual of International Symposium on Computer Architecture, Göteborg Sweden, pp. 230–239 (2001)
Weiss, S., Smith, J.E.: Instruction Issue Logic for Pipelined Supercomputers. In: Proceedings of 11th Annual International Symposium on Computer Architecture, pp. 110–118 (1984)
Sato, T., Nakamura, Y., Arita, I.: Revisiting Direct Tag Search Algorithm on Superscalar Processors. In: Workshop Complexity-Effective Design, ISCA (2001)
Buyoktusunoglu, A., Shuster, S.E., Brooks, D., Bose, P., Cook, P.W., Albonesi, D.H.: An Adaptive Issue Queue for Reduced Power at High Performance. In: Workshop on Power Aware Computer Systems, in conjunction with ASPLOS-IX (November 2000)
Moshnyaga, V.G.: Reducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage Supply. In: Workshop on Complexity Effective Design (June 2001)
Kukut, G., Ghose, K., Ponomarev, D.V., Kogge, P.M.: Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors. In: Proceedings of International Symposium on Low Power Electronics and Design, Huntington Beach California, USA (August 2001)
Ernst, D., Austin, T.: Efficient Dynamic Scheduling Through Tag Elimination. In: Proceedings of 29th Annual of International Symposium on Computer Architecture (2002)
Huang, M., Renau, J., Torrellas, J.: Energy-Efficient Hybrid Wakeup Logic. In: Proceedings of ISLPED, Monterrey California, USA, August 2002, pp. 196–201 (2002)
Goshima, M., Nishino, K., Nakashima, Y., ichiro Mori, S., Kitamura, T., Tomita, S.: A high-Speed Dynamic Instructions Scheduling Scheme for Superscalar Processors. In: Proceedings of 34th Annual International Symposium on Microarchitecture (2001)
Farrell, J.A., Fisher, T.C.: Issue Logic for a 600-Mhz Out-of-Order Execution Microprocessors. IEEE Journal of Solid State Circuits 33(5), 707–712 (1998)
Raasch, S.E., Binkert, N.L., Reinhardt, S.K.: A Scalable Instruction Queue Design Using Dependence Chains. In: Proceedings of 29th Annual of International Symposium on Computer Architecture, pp. 318–329 (2002)
Villa, L., Zhang, M., Asanovic, M.K.: Dynamic Zero Compression for Cache Energy Reduction, Micro-33 (December 2000)
Moshnyaga, V.G.: Energy Reduction in Queues and Stacks by adaptive Bit-width Compression. In: Proceedings of International Symposium on Low Power Electronics and Design, Huntington Beach California, USA, (August 2001), pp. 22–27 (2001)
Franklin, M., Sohi, G.S.: The Expandable Split Window Paradigm for Exploiting Fine Grain Parallelism. In: Proceedings of 19th Annual of International Symposium on Computer Architecture, pp. 58–67 (1992)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proceedings of 27th Annual International Symposium on Computer Architecture (June 2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ramírez, M.A., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M. (2003). A Simple Low-Energy Instruction Wakeup Mechanism. In: Veidenbaum, A., Joe, K., Amano, H., Aiso, H. (eds) High Performance Computing. ISHPC 2003. Lecture Notes in Computer Science, vol 2858. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39707-6_8
Download citation
DOI: https://doi.org/10.1007/978-3-540-39707-6_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20359-9
Online ISBN: 978-3-540-39707-6
eBook Packages: Springer Book Archive