Logic and Architecture Synthesis

1. Front Matter

   Pages N1-xii

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2. Logic Minimization Based on BDD

   1. Front Matter

      Pages 1-1

      PDF

   2. Boolean Optimization Using Implicit Techniques

      • F. Poirot, G. Tarroux, R. Roane

      Pages 3-14

   3. Multiple-Level Logic Optimization with Boolean Relations

      • Bernd Wurth, Norbert Wehn

      Pages 15-25

   4. BONSAI: A pragmatic approach to Logic Synthesis and Formal Verification

      • H. N. Nguyen, L. Ducousso

      Pages 26-37

3. Cell Assignment Based on BDD

   1. Front Matter

      Pages 39-39

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   2. Combined approach of ROBDDs and structural analysis in the mapping and matching of logic functions

      • A. M. Trullemans, R. Jacobi, Q. Zhang

      Pages 41-56

   3. Efficient ROBDD based computation of common decomposition functions of multi-output boolean functions

      • Christoph Scholl, Paul Molitor

      Pages 57-63

   4. Circuit depth optimization by BDD based function decomposition

      • Alexander I. Kornilov, Tatiana Yu Isaeva

      Pages 64-69

   5. Symmetry Based Variable Ordering for ROBDDs

      • Dirk Möller, Paul Molitor, Rolf Drechsler

      Pages 70-81

4. Partitioning and Clustering for Programmable Devices

   1. Front Matter

      Pages 83-83

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   2. Circuit clustering and partitioning for system implementations

      • Ulrich Weinmann, Wolfgang Rosenstiel

      Pages 85-96

   3. Circuit Partitioning For FPGAs

      • G. Saucier, D. Brasen, J. P. Hiol

      Pages 97-106

5. Logic Synthesis for Programmable Devices

   1. Front Matter

      Pages 107-107

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   2. Balanced multilevel decomposition and its applications in FPGA-based synthesis

      • T. Łuba, H. Selvaraj, M. Nowicka, A. Kraśniewski

      Pages 109-115

   3. Disjoint Decomposition for LUT FPGA Synthesis

      • Ulf Schlichtmann

      Pages 116-123

   4. Performance Comparison of Logic Block Units Implemented in FPGA’s Families

      • M. Robert, L. Torres, F. Moraes, D. Auvergne

      Pages 124-135

6. Structural Optimization

   1. Front Matter

      Pages 137-137

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   2. Area Optimization of Bit-Parallel Custom Data Paths

      • Z. Sahraoui, L. Rijnders, J. Vanhoof, I. Bolsens, H. De Man

      Pages 139-150

   3. DataPath regularity extraction

      • R. X. T. Nijssen, J. A. G. Jess

      Pages 151-157

This book describes several methods and systems solving one of the highlighted problems within computer aided design, namely architectural and logic synthesis. The book emphasises the most recent technologies in high level synthesis, concentrating on applicative studies and practical constraints or criteria during synthesis. Logic and Architecture Synthesis concentrates on the practical problems involving automatic synthesis of designs. It is essential reading for researchers and CAD Managers working in this area.

• ASIC
• CAD
• Design
• FPGA
• Field Programmable Gate Array
• RAM
• ROM
• VHDL
• VLSI
• algorithms
• architecture
• metal-oxide-semiconductor transistor
• microprocessor
• optimization
• static-induction transistor

• Institut National Polytechnic de Grenoble, Grenoble, France

  Gabrièle Saucier, Anne Mignotte

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