Abstract
In this paper, an FPGA based architecture for stereo vision is presented. The architecture provides a high-density disparity map in real time. The architecture is based on area comparison between an image pair using the sum of absolute differences. The architecture scans the input images in partial columns, which are then processed in parallel. The system performs monolithically on a pair of images in real time. An extension to the basic architecture is proposed in order to compute disparity maps on more than 2 images.
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Arias-Estrada, M., Xicotencatl, J.M. (2001). Multiple Stereo Matching Using an Extended Architecture. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_21
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DOI: https://doi.org/10.1007/3-540-44687-7_21
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